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rev. 1.5 6/08 copyright ? 2008 by silicon laboratories si5020 . si5020 siphy? m ulti -r ate sonet/sdh c lock and d ata r ecovery ic features complete high-speed, lo w-power, cdr solution includes the following: applications description the si5020 is a fully-int egrated low-power clock and data recovery (cdr) ic designed for high-speed serial communication systems. it extracts timing information and data from a se rial input at oc-4 8/12/3, stm-16/4/1, or gigabit ethernet (gbe) rates. support for 2.7 gbps data streams is also provided for oc-48/stm-16 applicati ons that employ forward error correction (fec). dspll technology eliminates sensitive noise entry points, making the pll le ss susceptible to board-level interaction and helping to ensure optimal jitter performance. the si5020 represents a new standard in low jitter, low power, and small size for high-speed cdrs. it operates from a single 2.5 v supply over the industrial temperature range (?40 to 85 c). functional block diagram ? supports oc-48/12 /3, stm-16/4/1, gigabit ethernet, and 2.7 gbps fec ? low power?270 mw (typ oc-48) ? small footprint: 4 x 4 mm ? dspll? eliminates external loop filter components ? 3.3 v tolerant control inputs ? exceeds all sonet/sdh jitter specifications ? jitter generation 2.9 mui rms (typ) ? device powerdown ? loss-of-lock indicator ? single 2.5 v supply ? sonet/sdh/atm routers ? add/drop multiplexers ? digital cross connects ? gigabit ethernet interfaces ? sonet/sdh test equipment ? optical transceiver modules ? sonet/sdh regenerators ? board level serial links dspll tm phase-locked loop retimer buf buf buf din + din ? rext lol 2 refclkin + refclkin ? ratesel1-0 2 dout + dout ? clkout + clkout ? pwrdn/cal 2 2 bias 2 ordering information: see page 18. pin assignments si5020 gnd pad connection 15 14 13 12 11 pwrdn dout+ vdd dout? vdd 1 2 3 4 5 vdd gnd refclk? rext refclk+ 20 19 18 17 16 ratesel1 ratesel0 clkout? clkout+ gnd 6 7 8 9 10 lol gnd din+ din? vdd top view
si5020 2 rev. 1.5
si5020 rev. 1.5 3 t able of c ontents section page 1. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1. dspll ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2. pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3. multi-rate operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.4. reference clock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5. lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.6. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7. powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 4.8. device grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.9. bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.10. differential input ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.11. differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. pin descriptions: si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. package outline: si5010- bm/gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. 4x4 mm 20l qfn recommended pcb lay out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
si5020 4 rev. 1.5 1. detailed block diagram pwrdn/cal calibration din+ din? clkout+ clkout? dout+ dout? lol refclk+ refclk? ratesel1-0 retime bias generation rext din+ refclk+ ratesel1-0 retime retime bias generation bias generation 2 phase detector phase detector phase detector a/d dsp vco clk divider n lock detector c c
si5020 rev. 1.5 5 2. electrical specifications figure 1. differential voltage measurement (din, refclk, dout, clkout) figure 2. differential clock to data timing figure 3. differential dout and clkout rise/fall times table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 25 85 c si5020 supply voltage 2 v dd 2.375 2.5 2.625 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 2. the si5020 specifications are guarant eed when using the recommended application circuit (including component tolerance) shown in "typical application schematic" on page 10. v is v id ,v od (v id = 2 v is ) differential i/os differential voltage swing single-ended voltage differential peak-to-peak voltage signal+ signal? (signal+) ? (signal?) v icm , v ocm v t dout t c-d clkout dout, clkout t f t r 80% 20%
si5020 6 rev. 1.5 table 2. dc characteristics (v dd = 2.5 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current oc-48 and fec (2.7 ghz) gbe oc-12 oc-3 i dd ? ? ? ? 108 113 117 124 122 127 131 138 ma power dissipation oc-48 and fec (2.7 ghz) gbe oc-12 oc-3 p d ? ? ? ? 270 283 293 310 320 333 344 362 mw common mode input voltage (din, refclk)* v icm varies with v dd ?.80xv dd ?v single-ended input voltage (din, refclk)* v is see figure 1 200 ? 750 mv pp differential input voltage swing (din, refclk)* v id see figure 1 200 ? 1500 mv pp input impedance (din, refclk)* r in line-to-line 84 100 116 differential output voltage swing (dout) oc48/12/3 v od 100 load line-to-line 780 990 1260 mv pp differential output voltage swing (clkout) oc48/12/3 v od 100 load line-to-line 550 900 1260 mv pp output common mode voltage (dout,clkout) v ocm 100 load line-to-line ?v dd ? 0.23 ?v output impedance (dout,clkout) r out single-ended 84 100 116 output short to gnd (dout,clkout) i sc(?) ?2531ma output short to v dd (dout,clkout) i sc(+) ?17.5 ?14.5 ? ma input voltage low (lvttl inputs) v il ?? .8v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ??10 a input high current (lvttl inputs) i ih ??10 a output voltage low (lvttl outputs) v ol i o =2ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o =2ma 2.0 ? ? v input impedance (lvttl inputs) r in 10 ? ? k pwrdn/cal leakage current i pwrdn v pwrdn 0.8 v 15 25 35 a *note: the din and refclk inputs may be driven differentially or single-endedly. when driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (vid min) and the unused input must be ac coupled to ground. wh en driving differentially, the difference between the positive and negative input signals must exceed vid min. (each individ ual input signal needs to swing only half of this range.) in either case, the voltage applied to any individual pin (d in+, din?, refclk+, or refc lk?) must not exceed the specified maximum input voltage range (vis max).
si5020 rev. 1.5 7 table 3. ac characteristics (clock & data) (v a 2.5 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit output clock rate f clk .15 ? 2.7 ghz output rise/fall time (differential) t r, t f figure 3 ? 80 110 ps clock to data delay fec (2.7 ghz) oc-48 gbe oc-12 oc-3 t c-d figure 2 225 225 460 835 4040 250 250 500 880 4090 270 270 540 930 4140 ps input return loss 100 khz?2.5 ghz 2.5 ghz?4.0 ghz ? ? 16 13 ? ? db db table 4. ac characteristics (pll characteristics) (v a 2.5 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit jitter tolerance (oc-48)* j tol(pp) f = 600 hz 40 ? ? ui pp f = 6000 hz 4 ? ? ui pp f = 100 khz 4 ? ? ui pp f=1 mhz 0.4 ? ? ui pp jitter tolerance (oc-12 mode) * j tol(pp) f = 30 hz 40 ? ? ui pp f = 300 hz 4 ? ? ui pp f=25 khz 4 ? ? ui pp f = 250 khz 0.4 ? ? ui pp jitter tolerance (oc-3 mode) * j tol(pp) f = 30 hz 60 ? ? ui pp f = 300 hz 6 ? ? ui pp f = 6.5 khz 6 ? ? ui pp f=65 khz 0.6 ? ? ui pp jitter tolerance (gigabit ethernet) receive data total jitter to l e r a n c e t jt(pp) ieee 802.3z clau se 38.68 600 ? ? ps jitter tolerance (gigabit ethernet) receive data dete rministic jitter to l e r a n c e d jt(pp) ieee 802.3z clau se 38.69 370 ? ? ps rms jitter generation * j gen(rms) with no jitter on serial data ? 2.9 5.0 mui peak-to-peak jitter generation * j gen(pp) with no jitter on serial data ? 25 55 mui
si5020 8 rev. 1.5 jitter transfer bandwidth * j bw oc-48 mode ? ? 2.0 mhz oc-12 mode ? ? 500 khz oc-3 mode ? ? 130 khz jitter transfer peaking * j p ? 0.03 0.1 db acquisition time t aq after falling edge of pwrdn/cal 1.45 1.5 1.7 ms from the return of valid data 40 60 150 s input reference clock duty cycle c duty 40 50 60 % reference clock range 19.44 ? 168.75 mhz input reference clock frequency to l e r a n c e c tol ?100 ? 100 ppm frequency difference at which receive pll goes out of lock (refclk compared to the divided down vco clock) lol 450 600 750 ppm frequency difference at which receive pll goes into lock (ref- clk compared to the divided down vco clock) lock 150 300 450 ppm *note: bellcore specifications: gr-253-core, i ssue 3, september 2000. using prbs 2 23 ? 1 data pattern. table 4. ac characteristics (pll characteristics) (continued) (v a 2.5 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit
si5020 rev. 1.5 9 table 5. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 2.8 v lvttl input voltage v dig ?0.3 to 3.6 v differential input voltages v dif ?0.3 to (v dd + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k )1 k v note: permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 38 c/w
si5020 10 rev. 1.5 3. typical application schematic si5020 lvttl control inputs loss-of-lock indicator lol high-speed serial input system reference clock din+ din? refclk+ refclk? rext vdd gnd dout+ dout? clkout+ clkout? recovered data recovered clock 0.1 f 2200 pf vdd 10 k ratesel1-0 pwrdn/cal 2 20 pf
si5020 rev. 1.5 11 4. functional description the si5020 utilizes a pha se-locked loop (pll) to recover a clock synchronous to the input data stream. this clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (cml) drivers. optimal jitter performance is obtained by using silicon laboratories' dspll technology to eliminate the noise entry points caused by external pll loop filter components. 4.1. dspll ? the pll structure (shown in figure 1 on page 5) utilizes silicon laboratories ' dspll technology to eliminate the need for external loop filter components found in traditional pll implementations. this is achieved by using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the volta ge-controlled oscillator (vco). because external loop filter components are not required, sensitive noise ent ry points are eliminated, making the dspll less susceptible to board-level noise sources that make sone t/sdh jitter compliance difficult to attain. 4.2. pll self-calibration the si5020 achieves opti mal jitter performance by using self-calibration circ uitry to set the loop gain parameters within the dspll. for the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 v when calibration occurs. for best performance, the user shoul d force a self-calibration once the supply has stabilized on powerup. a self-calibration can be initiated by forcing a high-to- low transition on the powerdown control input, pwrdn/ cal, while a valid referenc e clock is supplied to the refclk input. the pwrdn/cal input should be held high at least 1 s before transitioning low to guarantee a self-calibration. seve ral application circuits that could be used to initiate a power-on self-calibration are provided in silicon laboratories? ?an42: controlling dspll? self-calibration for the si5020/5018/5010 cdr devices and si531x clock multiplier/regenerator devices.? 4.3. multi-rate operation the si5020 supports clock and data recovery for oc-48 and stm-16 data streams. in addition, the pll was designed to operate at data rates up to 2.7 gbps to support oc-48/stm-16 applications that employ forward error correction (fec). multi-rate operation is ac hieved by configuring the device to divide down the output of the vco to the desired data rate. the divide factor is configured by the ratesel0-1 pins. the ratesel0-1 configuration and associated data rates are given in table 7. 4.4. reference clock detect the si5020 cdr requires an external reference clock applied to the refclk input for normal device operation. when refclk is absent, the lol alarm will always be asserted when it has been determined that no activity exists on refclk, indicating the frequency lock status of the pll is unknown. additionally, the si5020 uses the reference clock to center the vco output frequency so that clock and data can be recovered from the input data stream. the device self configures for operation with one of three reference clock frequencies. this eliminates the need to externally configure the device to operate with a particular reference clock. the reference clock centers the vco for a nominal output of between 2.5 ghz and 2.7 ghz. the vco frequency is centered at 16, 32, or 128 times the reference clock frequency. detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal vco output. approximate reference clock frequencies for some target applications are given in ta b l e 8 . table 7. multi-rate configuration ratesel [0:1] sonet/ sdh gigabit ethernet oc-48 with 15/14 fec clk divider 00 2.488 gbps ? 2.67 gbps 1 10 1.244 gbps 1.25 gbps ? 2 01 622.08 mbps ? ? 4 11 155.52 mbps ? ? 16 table 8. typical refclk frequencies sonet/sdh gigabit ethernet sonet/ sdh with 15/14 fec ratio of vco to refclk 19.44 mhz 19.53 mhz 20.83 mhz 128 77.76 mhz 78.125 mhz 83.31 mhz 32 155.52 mhz 156.25 mhz 166.63 mhz 16
si5020 12 rev. 1.5 4.5. forward erro r correction (fec) the si5020 supports fec in sonet oc-48 (sdh stm-16) applications for data rates up to 2.7 gbps. in fec applications, the appropriate reference clock frequency is determined by dividing the input data rate by 16, 32, or 128. for example, if an fec code is used that produces a 2.70 gbps data rate, the required reference clock would be 168.75, 84.375, or 21.09 mhz. 4.6. lock detect the si5020 provides lock-detect ci rcuitry that indicates whether the pll has achieved frequency lock with the incoming data. the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (refclk). if the recovered clock frequency deviates from that of the reference clock by the amount specified in table 4 on page 7, the pll is declared out-of-lock, and the loss-of- lock (lol) pin is asserted high. in this state, the pll will periodically try to reacquire lock with the incoming data stream. during reacquisiti on, the recovered clock may drift over a 600 ppm range relative to the applied reference clock, and the lol output alarm may toggle until the pll has reacquired frequency lock. due to the low noise and stability of the dspll, under the condition where data is removed from the inputs, there is the possibility that the pll will not drift enough to render an out-of-lock condition. if refclk is removed, the lol output alarm will always be asserted when it has been determined that no activity exists on refclk, indicating the frequency lock status of the pll is unknown. note: lol is not asserted during pwrdn/cal. 4.7. pll performance the pll implementation used in the si5020 is fully compliant with the jitter s pecifications proposed for sonet/sdh equipment by bellcore gr-253-core, issue 2, december 1995 and itu-t g.958. 4.7.1. jitter tolerance the si5020?s tolerance to input jitter exceeds that of the bellcore/itu mask shown in figure 4. this mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. note: there are no entries in the mask table for the data rate corresponding to oc-24 as th at rate is not specified by either gr-253 or g.958. figure 4. jitter tolerance specification 4.7.2. jitter transfer the si5020 is fully compliant with the relevant bellcore/ itu specifications related to sonet/sdh jitter transfer. jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a f unction of jitter frequency (see figure 5). these measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in figure 4. 4.7.3. jitter generation the si5020 exceeds all relev ant specifications for jitter generation proposed for sonet/sdh equipment. the jitter generation specificatio n defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. the si5020 typically generates less than 3.0 mui rms of jitter when presented with jitter-free input data. f0 f1 f2 f3 ft frequency 0.15 1.5 15 sinusoidal input jitter (ui p-p) slope = 20 db/decade sonet data rate f0 (hz) f1 (hz) f2 (hz) f3 (khz) ft (khz) oc- 12 oc- 3 10 10 30 30 300 300 25 6.5 250 65 oc- 48 10 600 6000 1000 1000
si5020 rev. 1.5 13 figure 5. jitter transfer specification 4.8. powerdown the si5020 provides a powerdown pin, pwrdn/cal, that disables the output drivers (dout, clkout). when the pwrdn/cal pin is driven high, the positive and negative terminals of clkout and dout are each tied to vdd through 100 on-chip resistors. this feature is useful in reducing power consumption in applications that employ redundant serial channels. when pwrdn/cal is released (set to low) the digital logic resets to a known initia l condition, recalibrates the dspll, and will begin to lock to the data stream. 4.9. device grounding the si5020 uses the gnd pad on the bottom of the 20- pin micro leaded package (mlp) for device ground. this pad should be connected directly to the analog supply ground. see figures 10 and 11 for the ground (gnd) pad location. 4.10. bias generation circuitry the si5020 makes use of an external resistor to set internal bias currents. the external resistor allows precise generation of bias cu rrents, which significantly reduces power consumption versus traditional implementations that use an internal resistor. the bias generation circuitry requires a 10 k (1%) resistor connected between rext and gnd. 4.11. differential input circuitry the si5020 provides differential inputs for both the high- speed data (din) and the reference clock (refclk) inputs. an example termination for these inputs is shown in figure 6. in applications where direct dc coupling is possible, the 0.1 f capacitors may be omitted. the din and refclk input amplif iers require an input signal with a minimum differential peak-to-peak voltage listed in table 2 on page 6. figure 6. input termination for din and refclk (ac coupled) 0.1 db jitter trans f er fc frequency 20 db/decade slope fc (khz) sonet data rate oc-48 oc-12 oc-3 2000 500 130 acceptable range differential driver si5020 0.1 f 0.1 f zo = 50 zo = 50 rfclk + rfclk ? 2.5 k 2.5 k 10 k 10 k 102 vdd gnd
si5020 14 rev. 1.5 figure 7. single-ended input termination for refclk (ac coupled) figure 8. single-ended input termination for din (ac coupled) 0.1 f clock source si5020 0.1 f zo = 50 refclk + refclk ? 2.5 k 2.5 k 10 k 10 k 100 gnd vdd 102 0.1 f clock source si5020 0.1 f zo = 50 din + din ? 2.5 k 2.5 k 10 k 10 k 100 gnd vdd 102
si5020 rev. 1.5 15 4.12. differential output circuitry the si5020 utilizes a curr ent mode logic (cml) architecture to outp ut both the recovered clock (clkout) and data (dout). an example of output termination with ac coupling is shown in figure 9. in app lications in which direct dc coupling is poss ible, the 0.1 f capacitors may be omitted. the differential peak-to-peak voltage swing of the cml architecture is listed in table 2 on page 6. figure 9. output termination for dout and clkout (ac coupled) dout ?, clkout ? 0.1 f 0.1 f zo = 50 zo = 50 si5020 vdd vdd 100 100 vdd vdd dout +, clkout + 50 50
si5020 16 rev. 1.5 5. pin descriptions: si5020 figure 10. si5020 pin configuration table 9. si5020 pin descriptions pin # pin name i/o signal level description 1 rext external bias resistor. this resistor is used by onboard circuitry to estab- lish bias currents within the device. this pin must be connected to gnd through a 10 k ( 1 %) resis- tor. 4 5 refclk+ refclk? isee table2 differential reference clock. the reference clock sets the initial operating fre- quency used by the onboard pll for clock and data recovery. additionally, the re ference clock is used to derive the clock output when no data is present. 6lololvttl loss-of-lock. this output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in table 4 on page 7. 9 10 din+ din? isee table2 differential data input. clock and data are recovered from the differential signal present on these pins. 12 13 dout? dout+ ocml differential data output. the data output signal is a retimed version of the data recovered from the signal present on din. it is phase aligned with clkout and is updated on the rising edge of clkout. gnd pad connection 15 14 13 12 11 pwrdn dout+ vdd dout? vdd 1 2 3 4 5 vdd gnd refclk? rext refclk+ 20 19 18 17 16 ratesel1 ratesel0 clkout? clkout+ gnd 6 7 8 9 10 lol gnd din+ din? vdd
si5020 rev. 1.5 17 15 pwrdn/cal i lvttl powerdown. to shut down the high-speed outputs and reduce power consumption, hold this pin high. for normal operation, hold this pin low. calibration. to initiate an internal se lf-calibration, force a high- to-low transition on this pin. (see "pll self-calibra- tion" on page 11.) note: this input has a weak internal pulldown. 16 17 clkout? clkout+ ocml differential clock output. the output clock is recove red from the data signal present on din. in the absence of data, the output clock is derived from refclk. 19 20 ratesel0 ratesel1 ilvttl data rate select. these pins configure the onboard pll for clock and data recovery at one of four user selectable data rates. see table 7 for configuration settings. note: these inputs have weak internal pulldowns. 2, 7, 11, 14 vdd 2.5 v supply voltage. nominally 2.5 v. 3, 8, 18, and gnd pad gnd gnd supply ground. nominally 0.0 v. the gnd pad found on the bottom of the 20-pin micro leaded package (see figure 11) must be connected directly to supply ground. table 9. si5020 pin descriptions (continued) pin # pin name i/o signal level description
si5020 18 rev. 1.5 6. ordering guide 7. top mark part number package voltage pb-free temperature si5020-x-gm 20-lead qfn 2.5 yes ?40 to 85 c 1. ?x? denotes product revision. 2. add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. these devices use a nipdau pre-plated finish on the leads that is fully rohs6 compliant while being fully compatible with both leaded and lead-free card assembly processes. silicon labs part number die revision (r) assembly date (yww) si5020-b-gm b y = last digit of current year ww= work week
si5020 rev. 1.5 19 8. package outline figure 11 illustrates the package details for the si5020. table 10 lists the values for th e dimensions shown in the illustration. figure 11. 20-pin quad flat no-lead (qfn) table 10. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 e2 1.95 2.10 2.25 a1 0.00 0.02 0.05 l 0.50 0.60 0.70 b 0.18 0.25 0.30 0 ? 12 c??0.60 aaa 0.10 d 4.00 bsc bbb 0.10 d2 1.95 2.10 2.25 ccc 0.08 e 0.50 bsc ddd 0.10 e 4.00 bsc eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vggd-1. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5020 20 rev. 1.5 9. 4x4 mm 20l qfn recommended pcb layout symbol parameter dimensions min nom max a pad row/column width/length 2.23 2.25 2.28 d thermal pad width/height 2.03 2.08 2.13 e pad pitch ? 0.50 bsc ? g pad row/column separation 2.43 2.46 2.48 r pad radius ? 0.12 ref ? x pad width 0.23 0.25 0.28 y pad length ? 0.94 ref ? z pad row/column extents 4.26 4.28 4.31 notes: 1. all dimensions listed are in millimeters (mm). 2. the perimeter pads are to be non-solder mask defined (n smd). solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad. 3. the center thermal pad is to be solder mask defined (smd). 4. thermal/ground vias placed in the center pad should be no less th an 0.2 mm (8 mil) diameter and tented from the top to prevent solder from flowing into the via hole. 5. the stencil aperture should match the pad size (1:1 ratio) fo r the perimeter pads. a 3x3 array of 0.5 mm square stencil openings , on a 0.65 mm pitch, should be used for the center thermal pad. 6. a stencil thickness of 5 m il is recommended. the stencil should be laser cut and electropolished, with trapezoidal walls to faci litate paste release. 7. a ?no-clean?, type 3 solder paste should be used for assembly. nitrogen purge during reflow is recommended. 8. do not place any signal or power pl ane vias in these ?keep out? regions. 9. suggest four 0.38 mm (15 mil) vias to the ground plane. see note 8 gnd pin gnd pin gnd pin see note 9
si5020 rev. 1.5 21 d ocument c hange l ist revision 1.2 to revision 1.3 ? added "top mark" on page 18. ? updated "package outline" on page 19. ? added "4x4 mm 20l qfn recommended pcb layout" on page 20. revision 1.3 to revision 1.4 ? made minor note corrections to "4x4 mm 20l qfn recommended pcb layout" on page 20. revision 1.4 to revision 1.5 ? added "top mark" on page 18. ? updated "ordering guide" on page 18. ? updated "package outline" on page 19.
si5020 22 rev. 1.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 7801 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: highspeed@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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